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Principal Engineer, R&D Engineering

JR-0000051018 Requisition #

Principal Hardware Research Engineer,

Next Gen Platform Technologies, Western Digital, Bangalore, India



SanDisk India DDC Pvt Ltd




Western Digital®


We deliver the possibilities of data. YOU define what’s possible.


Job Description and Responsibilities:


The WDC CTO office is a premier research group within Western Digital, with more than 140 researchers working across many technical fields including storage and systems architecture, operating systems, CPU technologies, machine learning and emerging non-volatile memories. The open position is within the CTO office, with focus on RISC-V based compute and coherent systems for next gen storage platforms.

The job opening is for a Research Engineering Member in our Multi-Core Cache Coherent Interconnect Project, based out of Bangalore. The main research theme of the group is microarchitecture and RTL level design of the enterprise/datacenter grade multi-core CPU sub-system based on open instruction set architectures such as RISC-V (see riscv.org) and analysis and development of open source cache coherency and on chip/off chip interconnect protocols. The main emphasis of the architecture will be enablement of novel memory centric architectures and memory interfaces, demonstrating and implementing unprecedented compute capability, memory bandwidth and scaling to 1PB scale. Project team roles will include architecture definintion, RTL development and verification.

We are looking for an experienced cache coherency verification engineer to be a part of our Hardware Research and Advanced Technology Group within Western Digital. If you are a passionate and dynamic individual, with at least 10+ years of industry experience with a background in verification of  processor caches, coherency fabrics or other processor subsystems, interested in working on the next generation platforms - we are interested in speaking with you. You will be part of a global R&D organization, working alongside some of our highly skilled and talented individuals, involved in the development of the our next gen compute CPU’s and storage systems for Western Digital


Minimum Qualifications:




·       Background in Computer Architecture, with implementation/micro-architecture level understanding of modern microprocessor and SOC systems required.

·       Hands on exposure to CPU Caches, Load Store Units and Cache Coherency microarchitecture verification is required. Familiarity with Coherency Protocols is needed.

·       Experience in building verification environments for CPU sub-systems and experience with unit or cluster verification is highly desirable. Should be proficient in Verilog/System Verilog with some experience with UVM being desirable.

·       Experience with “Test-Plan” development and “Coverage” based verification is a must. Must also be comfortable in writing/debugging assembly language and/or C based test cases. 

·       A Bachelores or a Masters Degree in Engineering from a college of repute.

·       10+ years of industry experience in the relevant domain.





·       Knowledge/experience with ASIC/SOC level verification of processors is a plus.

·       Familiarity with interconnect protocols like AXI, ACE, CCIX, OpenCAPI, etc. is a plus.

·       Good scripting skills in Perl/Python/Shell

·       Strong written and verbal communication skills is desired. Ability to articulate ideas and thoughts .




·       Strong Computer Architecture Background.

·       Experience in design or verification of CPU Load/Store Units, Caches, Coherency, TLB etc

·       Proficiency in System Verilog. Experience with UVM methodology is a plus.

·       Assembly and/or C programming.

·       Scripting in Perl/Python/Shell.




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